Previous Job
Digital Design Engineer
Ref No.: 16-00619
Location: San Jose, California
Position Type:Contract
Start Date / End Date: 10/05/2016 to 05/01/2017
Our Client is looking for a highly qualified RTL digital design engineer to join the FPGA
Architecture Development group. The right candidate will focus on full-chip RTL
development for next generation FPGA and programmable SoC products.
This individual will be primarily responsible for:
- Building full chip RTL connectivity models
- Integrating RTL components from multiple design teams
- Verifying that full chip models match architectural intent
- Developing custom tools and methodologies to improve development efficiency
and quality
The candidate must be able to work with team members in globally diverse
Qualifications - External
- BS in Electrical Engineering required, advanced degrees a plus
- 6+ years of industry experience and background in RTL-based (System Verilog)
high speed digital design
- Top-notch problem solving skills, working within complex systems
- Experience using FPGAs and understanding FPGA architectures
- Experience with all stages in the ASIC design flow including verification
methodologies and tools (UVM/OVM, Formal Checks, LINT tools, etc)
- Strong knowledge of Linux environment and scripting languages such as Perl or
- Experience using Revision Control tools - Subversion, RCS, CVS, or Perforce
- Excellent waveform debug skills using front end industry standard design tools
like VCS, NCSIM, or Verdi
- Good communication skills able to write design specifications, write test plans
and conduct peer reviews and the ability to work well in a global, multi-site team