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Physical Design Engineer
Ref No.: 20-00346
Location: Austin, Texas
AESI is looking for a Physical Design Engineer for one of our premier clients in the Austin, TX area. As our employee you qualify for our full benefits package. This position is a 6 month contract with the possibility for extension. 

Responsibilities:
  • This is a mid to senior level position where the candidate will be in an individual contributor role, tasked with driving synthesis, block and full chip implementation through sign-off with the latest industry P&R/STA flows and tools.
  • Significant block level floor-planning, implementing and optimizing the design to meet aggressive performance/power and area targets will be critical for success.
Requirements:
  • Hands-on responsibility from synthesis to place and route of a System-IP block through signoff flows including timing and physical verification
  • Synthesis, Floor plan, Place & Route in chip-level and hierarchical physical implementation environment
  • Running MBIST and DFT insertion into block, understanding impact of MBIST/Scan and debug logic is desirable
  • Interact with RTL counterpart to resolve design issues pertaining to block closure
  • Optimize GPU block to meet aggressive power/performance/area targets
Requirements:
  • BS in Electrical Engineering, Computer Engineer or similar fields
  • 5 + years of experience 
  • Solid understanding and working knowledge of the SOC/ASIC/GPU/CPU design flow with some experience in taping out designs
  • Hands-on experience with synthesis, block and full chip implementation with the latest industry P&R/STA flows and tools
  • Experience in block level floor-planning, implementing power grid and power/area/performance optimization
  • Strong scripting/programming skills in Tcl, Perl, Shell, and/or Python
  • Solid understanding of Electrical Engineering fundamentals, analytical aptitude and excellent attention to detail
  • Strong communication skills, team player working in collaborative work environment, discipline and planning
  • Ability to execute with high quality deliverable
Preferred Skills:
  • Experience with 16nm Finfet or smaller process nodes
  • Experience with design implementation of GPU blocks and standard industry standard tools is advantageous
  • Ability to read Verilog 
  • Hands-on experience with clock tree synthesis (CTS)
  • Sign-off experience with reliability, signal integrity, noise, timing, power, physical and DFM closure is an added advantage