Previous Job
Previous
Design Integration
Ref No.: 20-00334
Location: San Jose, California
AESI is looking for a Design Integration Engineer for one of our clients in the San Jose, CA area. This is a mid to senior level position where the candidate will be in an individual contributor role, tasked with driving the Integration efforts across various sub-blocks. This is a 6 month contract. As our employee, you qualify for our full benefits package. 

Key responsibilities include:
  • Engage in Lint, CDC & Spyglass Clean up with RTL Team
  • Automate day-to-day data gathering efforts
Requirements:
  • BSEE, Computer Engineer or comparable and 5 + years of experience with Verilog and System Verilog
  • 3 years of experience with Spyglass tools (Lint, CDC) and Spyglass DFT
  • Experience with Design Compiler synthesis
  • Experience with scripting languages (Perl/Tcl/Python)
  • Good written and verbal communication skills 
Preferred candidate will possess the following:
  • Experience in Python Pandas Data frames
  • Experience in Lint, CDC and Spyglass 
  • Scripting proficiency