Responsibilities:

• Advanced UVM based test bench development and debugging
• Define, document, develop and execute RTL verification test/coverage at system level
• Performance and power-aware verification
• Triage regressions, debug RTL designs in Verilog and SystemVerilog
• Assist in refining verification process, methodology, and metrics
• Verification of complex SoC projects from test bench dev to closure

Required Skills:

• BS Degree in Computer Science or other engineering discipine
• 2+ years' experience in design and verification experience
• Experience with Cadence, Synopsys, Mentor logic simulators
• Verification flow enhancements using Shell scripts, Python, or JavaScript
• Strong SystemVerilog skills

Desired Skills:

• Interconnect verification