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FPGA Design/Verification Engineer
Ref No.: 18-01417
Location: Sunnyvale, California
Position Type:Contract
Start Date: 02/23/2018
Job Category:IT - Infrastructure Other Skills
Position Description:
ASIC & FPGA development on R&D program. Junior engineer with experience developing, testing, and integrating digital signal processing (DSP), high speed digital design, high speed communication and system-on-chip (SOC) implemented on FPGA platforms. Develop more affordable ways to automate and develop scripts to improve FPGA development efforts. Experience with COTS based control platforms, networking equipment. Member of a small team to help develop test benches and troubleshoot technical issues in the lab. Works with general direction from technical leads. Contributor to complex systems employing high speed networking concepts. Provide support and technical direction to entry engineers. Contribute to design, simulation, verification, integration & test of complex, high speed products. Work to be performed with general technical oversight.

Skills Required:
FPGA & ASIC Design and Verification experience.
Language Proficient in VHDL/Verilog for FPGA Development.
FPGA Verification with OVM/UVM
Developing, testing, and integrating digital signal processing (DSP), high speed digital design, high speed communication or system-on-chip (SOC) implemented on FPGA platforms.
System Verilog programming experience.
Basic proficiency in C/C++ for embedded systems.
Strong lab integration and test skills.
Skills Preferred Experience with modern verification methodologies, including UVM and/or OVM.

Experience Preferred:
Experience Required Bachelors degree from an accredited college in a related discipline, or equivalent experience/combined education, with 2 years of professional experience; or no experience required with a related Masters degree.
Considered experienced, but still a learner.
Experience in developing FPGAs and/or ASICs for high-reliability applications including space environments.
Experience developing with Xilinx Virtex-5QV, Microsemi antifuse (RTSX and/or RTAX) and SoC (RTG4) devices and Xilinx 7-series or newer devices.
Experience with Mentor Graphics Modelsim or Questasim, Synopsys Synplify Pro, Xilinx ISE and/or Vivado, Microsemi Libero IDE and/or Libero SoC.
Familiarity with UVM-based functional verification concepts and methodologies, as they apply to design for test.
Experience evaluating IP cores from multiple vendors and performing trade studies to determine optimal solution.
Experience with AMBA architectures, embedded processors, and IP cores.
Experienced in writing VHDL for synthesis.