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Senior Engineer (JL=16) (662833)
Ref No.: 18-12418
Location: Santa Clara, California
Start Date / End Date: 10/14/2018 to 04/12/2019
Senior IC Layout Design Engineer
Client's analog team is seeking a Senior IC Layout Design engineer, who will be responsible for IC Layout Design of high speed mixed-signal products. The candidate is expected to be self driven, having experience in the physical design and verification of high performance analog circuit with state-of-art CMOS process technologies.
Minimum Requirement
6+ years layout design and verification experience in high speed and high performance analog/mixed signal layout design and IC Layout Design, including PLL, Bandgap reference, SerDes and custom I/Os
Experience with CMOS 40nm, 28nm and FIN FET (16nm and under) processes, including rules and verification flows
Comfortable for floor planning based on discussion with circuit designers
Experience on both circuit level design and chip level integration
Knowledgeable with PDK and p-cells
Expert in using CAD tools, including Cadence Virtuoso 6.15, Mentor Caliber DRC/LVS.
Understand the basic trade-offs of layout efficiency and performance.
Basic knowledge of ESD/Latch-up.
Good communication skill with layout and circuit design engineers.