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Design Verification Senior Engineer (554235)
Ref No.: 17-08668
Location: Santa Clara, California
Start Date / End Date: 10/30/2017 to 10/28/2018
Description:
We are looking for a contractor to help the Pre-Silicon design verification team in verifying the core-level memory-subsystem blocks.

The engineer will be responsible for:
1.Developing a test bench (various components, stub model, constrained random test-generator, checkers) for verifying memory-subsystem block. This block is within the CPU core.
2.Verifying the related RTL block using this developed testbench
3.Responsible for coverage for the related block

Minimum Requirements:
1.(Mandatory) Candidate must have developed at least one test-bench from scratch.
2.(Mandatory) Candidate must have a solid understanding and hands on experience with System Verilog, uvm, Verilog.
3.(Highly desirable) Candidate must have worked on verifying one of the following blocks – Level 2 Cache, Load/Store Unit, Data Cache Unit.
4.Candidate should have a good understanding of how CPU core works.
5.Maximum 4-5 Years of experience