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Design Verification Engineer
Ref No.: 19-10241
Location: Santa Clara, California
Design Verification Engineer
Santa Clara, CA AND Hudson, MA
interview: Phone/video/ONSITE interview if LOCAL
Duration: 12 months

Job Responsibility
Knowledge of Code coverage using features in existing simulators or stand-alone tools like Surecov, HDL score etc.
Working on full chip verification and OVM/UVM Methodology, System Verilog is a must with 3+years of recent work experience, worked on passing test cases, test benches, Building environment.
Knowledge of Functional coverage using HVL language features or assertions a plus.
Should be ARM based SoC verification only. No need to mention tools.
Proficiency in one scripting language like Perl, C++, Python, Unix Make, Unix Shell Scripts etc.
Experience on verification of USB Type-C PHYs or any other high speed PHYs

Desired Skills & Experience:
Experience level 4 to 7 years.
Strong domain knowledge on one or more - PCIe,USB, Ethernet, ARM, AHB/AXI, AMBA, Networking, CPU, ARM, Graphics (DDR, PCIE, USB)
Should have worked on SOC verification on at least one project with constrained random methodology (OVM/UVM).
Good in concepts Code coverage and functional coverage.
Expertise in Verilog and / or VHDL is desired.
Strong in SV & OOPS
IP or SoC verification
Functional + code coverage
ARM based SoC verification
Capable of developing C tests
Working knowledge – SV/METH
Code coverage

B.Tech/B.E., in Electronics/Telecommunication, Electrical) OR (PG - M.Tech/M.E, in (Electrical, Electronics/Telecommunication)