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Physical Verification Engineer
Ref No.: 19-10232
Location: Palo Alto, California
Physical Verification Engineer 
interview process: Phone/video/ONSITE interview if LOCAL 
Location:Palo Alto, CA
duration: 6+ months 
No CPT/OPT

Hands-on experience in physical verification – DRC, LVS, ERC, ANT running and debugging in 7nm. 
Excellent understanding of the 7nm process technology and DRC rule interpretation. 
Expertise in LVS debugging – short isolation 
Experience with Cadence PVS tool is a plus (but not required). 
Need to work on-site (Palo Alto)