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CPU/L2/L3 Cache verification
Ref No.: 18-28323
Location: Raleigh, North Carolina
Job Overview:
In this role, you will be working on the verification of a high-performance, low-power ARM CPU and/or associated L2 and L3 caches employing leading-edge verification technologies to create low-power, high-performance products. You will collaborate with other engineering teams to complete solutions that address functional, performance, power, and cost requirements. In this role, you may be involved in any of the following: - Develop testbenches for verification of the CPU/L2/L3 - Generate and run testcases on logic simulation models - Run and debug tests to achieve architectural compliance - Work with scripting and tool infrastructure teams to improve verification productivity - Debug and correct failing testcases using simulation tools, debug tools, and programming skills - Develop a deep understanding of the architecture, micro-architecture, and RTL design-under-test - Document and implement testplans and testbench designs - Define and implement functional coverage - Analyze coverage results and address with testbench enhancements - Participate in testplan and testcode reviews with technical leads - Support Post Silicon verification and bring up
Minimum Qualifications:
We are looking for engineers that possess the following skills and a minimum of 5 years of experience: - Experience with RTL level CPU/L2 design verification - Experience with Perl or some similar scripting language - Experience with assembly language for ARM or other architectures - Knowledge of CPU architecture and some use of assembly language (especially RISC). - Experience using industry-standard RTL simulation and debug tools - Ability to debug Verilog RTL in a System Verilog/UVM environment - Excellent written and verbal communication skills - Excellent critical thinking and problem solving skills - Attention to detail, self-motivation and ability to influence teams without direct control. NOTE: New/recent college grads will not be considered without significant, relevant industry experience in microproceesor design/verification.
Preferred Qualifications:
Experience with micro-architecture of one or more of the following: - directed random verification of complex RISC microprocessors - load/store function, L2 and L3 caches, processor and system-level memory coherency -Experience with the specification and creation of design test benches using UVM, Verilog, or System Verilog -Experience with functional coverage driven verification
Education:
Client or EE with software/verification experience strongly preferred. New/recent grads not considered without significant relevant industry experience in microprocessor design/verification.