Previous Job
DFT Engineer
Ref No.: 18-26887
Location: San Diego, California
Job Overview:
The person hired in to this role will be contributing to DFT insertion and validation effort of complex RFFE core -Responsible for taking any or all of the following aspects to closure in a timely fashion. Analyze, propose best compression that can be achieved. Own and deliver scan insertion, validate equivalence check. Debug/resolve any DRC issues, identify solution and work with front-end team to ensure DFT DRCs are fixed. Analyzing and meeting ATPG coverage goals >99.5% for static and >90% for TDF. Own and deliver MBIST insertion, validate Memory test. Own RTL and Gate level simulations for Scan and Memory test vectors. Owns STA constraints and work with STA team to resolve timing violations. Support silicon bring-up and debug

Minimum Qualifications:
Minimum of 5+ year experience in the area of ASIC/DFT -In depth knowledge of DFT concepts -In depth knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis -In depth knowledge and hands on experience in MBIST insertion and Memory test validation -Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations -Expertise in scripting languages such as perl, shell, etc. -Experience in RTL and Gate level simulations of scan and MBIST test vectors -Knowledge of equivalence check, DFT DRC rules both in RTL lint tool (like spyglass) and ATPG tool like (TetraMax/Tessent) -Working experience in Synopsis TetraMax/DFTMax and Cadence Encounter Test is a plus -Ability to work in an international team, dynamic environment -Ability to learn and adapt to new tools and methodologies. -Ability to do multi-tasking & work on several high priority designs in parallel. -Excellent problem solving skills

Preferred Qualifications:
Tools: Synopsys Tetramax/SMS, Mentor Fastscan/LV or Tessent MBIST. Understanding of core-based test methodology and scan isolation, knowledge in JTAG, Scan Compression, ATPG, Fault Simulation and at-speed testing

Must have BS in Electrical Engineering. Preferred MS in Electrical Engineering