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Digital SoC DFT Engineer
Ref No.: 18-26869
Location: San Diego, California
Hardware Digital: DFT Implementation
DFT/DFD (design for test/design for debug) implementation for low power, multi voltage designs employing scan/ATPG, memory BIST, I/O BIST, JTAG boundary scan
Bachelor's degree in Science, Engineering, or related field. 2+ years ASIC design, verification, or related work experience.
2+ years experience in the following: SOC DFT/DFD implementation, hands on experience with industry ATPG/memory BIST Tools: Synopsys Tetramax/SMS, Mentor Fastscan/LV or Tessent MBIST. Understanding of core-based test methodology and scan isolation, knowledge in JTAG, Scan Compression, ATPG, Fault Simulation and at-speed testing
Required: Bachelor's, Electrical Engineering
3 total openings - Seeking ENG 2 level candidates (4-8 yrs industry exp) - please ensure submitted candidates align to this level.