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CPU custom TLB/cache array and circuit design
Ref No.: 18-22941
Location: Raleigh, North Carolina
Title: CPU custom TLB/cache array and circuit design
Location: Raleigh NC
Duration: 9 months

Job Overview:

This role will involve design and analysis of custom array macros relating to high performance CPU. You will be part of a team working towards the release of an advanced processor SOC in Qualcomm's roadmap. You will work closely with mask designers to optimize performance for an aggressive technology node.

Minimum Qualifications:
- Experienced in CPU custom TLB/cache array and circuit design
- Knowledgeable with timing rule generation & characterization
- Knowledgeable in circuit design margin analysis - Knowledgeable in Cadence Virtuoso, Synopsis Customsim, ESP, Verilog and Totem tools
- Strong with circuit simulation and analysis tools, scripting, automation
- Experience working closely to provide direction to mask designers for optimizations - Experience with TSMC technologies
- Experience with 7nm technology, layout effects, reliability analysis
- Strong team player
- Bachelor's degree + min 5 years experience


Preferred Qualifications:
Prefer Master's degree + 10 years experience Prefer prior experience with Qualcomm design environment

Education:
Emphasis in digital circuit design, SRAM array design, cache design would be preferred