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Physical Design and STA Engineer
Ref No.: 18-22833
Location: Santa Clara, California
Job Overview:
Be part of a physical design team responsible for :
To work with RTL, synthesis and dft team on understanding design in context of physical design timing closure including development of timing constraints required for implementation
To work with physical design engineers on timing closure including timing analysis and eco generation, signal integrity analysis
To do Floor planning, P&R, timing closure SI prevention/fixing, power planning, CTS, PV and I/R drop for Block as well as Top level MSM.

Minimum Qualifications:
at least 5 year experience in Physical Design and STA and timing closure
be expert and have good understanding of STA and timing closure methodologies and techniques hand-on experience in timing closure of complex design (IP and SoC level)
ability to write timing eco to close challenging timing violations
Good understanding of physical design flow and their impact on timing closure
ability to deal with MSM Top level complexity from FP, Placement, CTS, Routing and timing closure
must be able to take the Hardmacro through P&R from Netlist to GDS including timing closure and Physical verification

Preferred Qualifications:
Please see minimum qualifications.

Required: Bachelor's, Computer Engineering Preferred: Master's, Computer Engineering or equivalent experience