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Digital Physical Design Engineer
Ref No.: 18-22702
Location: San Diego, California
Our Digital Physical Design Team is responsible for the drive and execution of all phases of the complete netlist-to-GDSII flow for all embedded digital circuits in Analog IP. Design scope ranges from block-level to chip-level across many QC product lines, including modem, transceiver, power management, and RF front-end. Responsibilities: You will be part of a team responsible for the complete Physical Design Flow for embedded digital circuits. Tasks involved can be one or more of the following: Work with the design team on understanding in context of physical timing closure, including development of timing constraints required for implementation and signoff. Lead block- and chip-level signoff closure activities, including timing, physical verification, powergrid verification, logical equivalence, and power domain integrity . Develop new scripts/flows to improve implementation and closure processes. Complete netlist-to-GDSII implementation of embedded digital circuits. Implement and develop low-power implementation methods, including use of headswitches, clock gating, multi-vdd, and multi-vth Block- and chip-level floorplanning, powergrid, placement, CTS, P&R, PV, timing, and Signal Integrity Analysis. Work closely with analog design teams to implement highly-customized PNR solutions.
Minimum Qualifications:
Bachelor's degree and 5+ years experience in 4 or more of the following areas: Physical implementation (Floorplanning, CTS, STA) in advanced technologies STA tool and closure methodologies, including experience with Primetime and rapidly-advancing STA inputs Power grid, clock tree, and low-power reduction implementation methods Signal integrity and timing closure methodologies such as OCV/AOCV/Statistical Physical Verification, Conformal Low Power (CLP), IR drop analysis, Formal Verification Programming and scripting skills (Tcl, perl and/or C)
Preferred Qualifications:
Master's degree Power-aware yield estimation Vmin optimization Semi-custom of structured blocks Clock tree analysis and optimization Strong verbal and written communication skills
Education:
Required: Bachelor's, Computer Engineering and/or Computer Science and/or Electrical Engineering Preferred: Master's, Computer Engineering and/or Computer Science and/or Electrical Engineering