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DFT Engineer
Ref No.: 18-21736
Location: San Jose, California
Engineer will assist in DFT/scan development for server class device. The job requires experience in scan insertion, ATPG, simulation (non-timing and timing), iJTAG, TDF, silicon bring-up, Synopsys and Mentor (Tessent) toolsets, hierarchical DFT, TCL, PERL, Synopsys VCS and Mentor Questa, vector planning and release, must be very disciplined engineer able to handle multiple DFT assignments at the same time given that new development and bring-up of previous design always overlap
Minimum Qualifications:
5 years experience in relevant field 5 five years of experience in DFT/ATPG field driving scan insertion, DRC, simulation. Strong hardware skills required. Strong scripting experience using TCL/PERL.
Preferred Qualifications:
10 years experience in relevant field, proven experience with very large designs, independent ownership of DFT insertion and simulation for large cores, independent ownership of DFT insertion and simulation for chip top or a large design, Mentor LVMBIST experience
Education:
Candidate must have undergraduate degree in Electrical Engineering. A Master's in EE with a focus on DFT is preferred.