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SOC Low Power Design Engineer
Ref No.: 18-20489
Location: San Diego, California
Job Overview:
The Global SoC Power team is responsible for low power implementation and power analysis at SoC level design.
This includes defining low power requirements implementation of digital, mixed-signal circuits and systems that are integrated into System-on-Chip (SoC).
Power analysis responsibilities includes SoC Baseline Power rollup, Core Power Requirements, Power Models for UC (use-case) power rollup at chipset level.
The ideal candidate should be familiar with low power design techniques and power structural verification.
Experienced in using Cadence Conformal Low Power tool for structural power verification and PrimeTime Power Analysis Tool is required.


Minimum Qualifications:
Bachelor's degree in Electrical or Computer Engineering plus: ASIC frontend development Logic design, RTL coding, verification, synthesis, and timing closure Hardware description languages (Verilog, VHDL, System Verilog) Power-aware implementation flow, including UPF/CPF/Conformal Low Power Check Power simulation/analysis tool (PtPx/PowerArtist)

Preferred Qualifications:
PREFERRED QUALIFICATION: Master's degree in Electrical or Computer Engineering Experience with/in: Experienced in low power design optimization techniques Familiarity of power islands, power gating, power sequencing and multi-voltage domain design Familiarity of overall SoC Infrastructure - Busses, CPUs, I/Os and DFT Components Scripting and coding with Perl/Tcl

Education:
Required: Bachelor's, Electrical Engineering