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Synthesis, STA, FV and ECO Digital ASIC Engineer
Ref No.: 18-18929
Location: San Diego, California
Title: Synthesis, STA, FV and ECO Digital ASIC Engineer
Location: San Diego CA
Duration: 6 months


Job Overview:
Top level monster SoC implementation bridging RTL and physical design including logic synthesis with Synopsys Design Compiler, formal verification, timing constraint creation + validation and functional ECO creation.

Minimum Qualifications:
Bachelor's degree in a relevant electronic/computer engineering field + 3 years experience in logic synthesis, formal verification, timing constraint creation/validation and/or functional ECO creation. Sorry - NO NEW GRADS.

Preferred Qualifications:
Master's degree in a relevant electronic/computer engineering field + 5 years experience in logic synthesis, formal verification, timing constraint creation/validation and/or functional ECO creation.

Education:
BSc BEng MSc MEng