Description: - RTL IP integration - Perform full system simulation - Map a new SOC design to a Xilinx FPGA platform (MCU, AHB, memory, custom logic) - FPGA Constraints, Synthesis, P&R, Floorplanning, Timing Closure - Low Power digital design - Provide lab support throughout project
Minimum Qualifications:
- FPGA experience - Xilinx, Vivado development suite - Verilog, SV, C code, UVM - ASIC flows: Synthesis, PLDRC, FV, CDC -Lab experience- effective debuggling and problem solving skills; familiarity with electric analyzers, signal generators - Excellent Technical Communications Skills (both written and verbal) - Ability to work in a Team Environment - Self Direction and Strong Time Management Skills
Preferred Qualifications:
- MS degree, 8+ years (ideally 8-10 years experience) - PERL - Clearcase
Education:
- BS/MS degree in EE/CS