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Design Verification Engineer
Ref No.: 18-16741
Location: Austin, Texas
CPU core design verification; ASIC Design Verification

Looking for strengthening RISC-V CPU core design verification effort. Candidates are expected to have strong previous experience and background in both UVM design verification of ASICs and CPUs, and other design verification methodologies as applied to CPUs and CPU cores. Previous RTL design experience, previous instruction set simulator experience, and co-simulation methodologies is considered a plus.

Monika Singh