Previous Job
Previous
Hardware Design Engineer
Ref No.: 18-16711
Location: San Diego, California
Job Overview:

Work with the graphics microarchitecture and physical design teams.
This position involves in-depth understanding of the ASIC design flow from RTL to GDS2 and the challenges posed by advanced technologies such as 7 FinFET.
The successful candidate will possess detailed understanding of RTL design, synthesis, static timing analysis, formal verification, physical design and ECO generation and verification.
Knowledge and experience of graphics design and development is a definite advantage: -
Implementation and delivery of GPU cores from RTL to GDSII
- Work with design team to create RTL builds
- Identify areas for flow and process improvements
- RTL synthesis using physically aware tools
- Formal Verification using industry standard tools for RTL-netlist and netlist-netlist checks
- Close design timing by running static timing analysis and constraint development
- Generate and verify ECOs for functional and timing fixes, working closely with the physical design team
- Manage design goals in power, performance and area


Minimum Qualifications:
- At least 5 years relevant industry experience
- Digital design and RTL development skills
- Expert level knowledge of synthesis, static timing, timing closure, constraints and formal verification
- Proficient in Synopsys Design Compiler tools, Conformal LEC, Synopsys Formality and Synopsys PrimeTime
- Physical design tool experience is desired but not required


Preferred Qualifications:
- Proficient in UNIX and Perl, TCL and shell scripting
- Excellent interpersonal and analytical skills with the ability to work independently
- Highly motivated, excellent team spirit, obession with deliverable quality and customer oriented


Education:
Required: Bachelor's, Electrical Engineering Preferred: Master's, Electrical Engineering