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Digital Physical Design Engineer
Ref No.: 18-16137
Location: San Diego, California

 Physical implementation (Floorplanning, CTS, STA) in advanced technologies STA tool and closure methodologies, including experience with Primetime and rapidly-advancing STA inputs Power grid, clock tree, and low-power reduction implementation methods Signal integrity and timing closure methodologies such as OCV/AOCV/Statistical Physical Verification, Conformal Low Power (CLP), IR drop analysis, Formal Verification Programming and scripting skills (Tcl, perl and/or C)
Preferred Qualifications:
Master's degree Power-aware yield estimation Vmin optimization Semi-custom of structured blocks Clock tree analysis and optimization Strong verbal and written communication skills
Education:
Required: Bachelor's, Computer Engineering and/or Computer Science and/or Electrical Engineering Preferred: Master's, Computer Engineering and/or Computer Science and/or Electrical Engineering