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Design Verification Engineer
Ref No.: 18-15801
Location: San Diego, California
Perform design verification of GNSS location cores and IP. Develop and write system verilog based tests using UVM. Debug RTL issues and provide feedback to designers. Provide support to SOC DV team during GNSS integration to SOC. Implement and debug Gate Level and Power Aware simulations. Work alongside other DV and design engineers for test planning and test implementation.
Minimum Qualifications:
BSEE with minimum 5 years experience. Have an extensive background in design verification work. Experience in verilog, systemverilog and UVM based test implementation. Experience in debugging RTL. Experience with the latest verification tools such as Synopsys VCS, Modelsim, Cadence, etc. Be able to implement UVM agents and sequences. Good communication skills.
Preferred Qualifications:
BSEE with minimum 10 years experience focused in design verification. Have implemented a UVM verification environment from the ground up. Have a background in hardware design.
Education:
Required: Bachelor's, Computer Engineering