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DDR PHY Timing engineer / STA Engineer
Ref No.: 18-13908
Location: San Diego, California
Title:                       DDR PHY Timing engineer
Work Location:     San Diego, CA
Duration :               5 months
Job Overview:
This position requires involvement in all aspects of front-end and physical design, guiding a cross-functional DDR PHY team on timing considerations from architecture through tapeout.


Minimum Qualifications:

3+ years of practical experience with static timing analysis(STA) and PrimeTime constraints development.
Relevant skillset:
1.VLSI circuits understanding, including Spice analysis.
2.DDR operation and timing considerations.
3.Unix/Perl/TCL scripting (must be comfortable with writing scripts)

Specific responsibilities may include:
1.Identification and analysis of design timing bottlenecks and mitigation solutions.
2.Guidance to front-end and physical teams on all aspects of timing considerations.
3.Development and support of PrimeTime STA timing constraints.
4.Execution of Star-RCXT/PrimeTime flow for analysis and sign-off.
5.Development of system timing budget and application to internal constraints.
6.Development of scripted automation for efficient data and waiver processing.


Preferred Qualifications:
see minimum qualifications. Excellent communication skills and ability to work efficiently with a global cross-functional team.

Education:
Required: Bachelor's, Electrical Engineering Preferred: Master's, Electrical Engineering