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Design Verification Engineer
Ref No.: 18-11296
Location: San Diego, California
 Seeking digital verification engineers for the mixed-signal ASICs that support mobile platforms for next generation 5G RFIC technologies.
Successful candidates will be working on the following:
- Block level digital IP verification using constraint
-random coverage methodologies at both RTL and Gate Level.
The skills involved includes SV/UVM/UVM_REG/Randomization/Coverage/SVA.

Minimum Qualifications:
3 years minimum experience and working knowledge of Object-Oriented SystemVerilog principles using UVM/OVM/VMM methodologies.

Preferred Qualifications:
Extensive hands on experience in verifying digital blocks, building UVM based TB, writing UVM sequences, constraint-random testcases, using regModel (UVM_REG) API, drivers, monitors, scoreboard, functional coverage (covergroups), assertions (SVA), simulations, regression, debug, bug reporting/tracking.
-Experience in debugging RTL & Gate level simulations

Required: Bachelor's, Electrical Engineering Preferred: Master's, Electrical Engineering or equivalent experience