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Physical verification engineer
Ref No.: 18-10581
Location: Santa Clara, California
Job Overview:
To submit and debug all caliber checks (LVS/DRC/ERC/PERC/DFM/ETC). To work with physical design engineers to provide feedback to fix database issues.
To edit cadence layout libraries using Cadence Virtuoso.

Minimum Qualification:
Good understanding of LVS/DRC/ERC/PERC concepts and hands-on experiences with Calibre tool and LVS/DRC/ERC/PERC debugging.
Can navigate/modify cadence libraries using virtuoso, with virtuoso editing expertise. Good understanding of 14nm and beyond process technologies

Required: Bachelor's, Computer Engineering Preferred: Master's, Computer Engineering or equivalent experience