Previous Job
ASIC Physical Design/STA Engineer
Ref No.: 18-10534
Location: Santa Clara, California

ASIC Physical Design/STA Engineer

Chip Level Static Timing Analysis, Constraints analysis and Timing closure activities including ECO implementation to fix timing issues on post route database

Strong STA skills including PrimeTime/PrimeTime SI timing analysis, Perl/tcl programming experience is a plus

EXPERIENCE AND EDUCATION: SoC Architecture; knowledge and hand-on experience from industry ASIC design flow including RTL coding, debugging/verification, and supporting synthesis and timing closure. Working knowledge of ARM cores and other I/O standard interfaces. An ideal candidate would also exhibit: Strong communication and documentation skills, Good organizational, time management and multitasking skills, Strong initiative and discipline to follow-through, Technical leadership