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RTL Design Engineer
Ref No.: 17-25805
Location: San Diego, California
The CPU team in Austin has an immediate opening for RTL design and integration. The ideal candidate should have at least 5 years experience in RTL implementation and system level debug. Understanding of ARM CPU and CPU subsystems would be preferable. Understanding of constrained random verification environments and the ability to write and debug testcases would be preferred.
Minimum Qualifications:
RTL Design Using System Verilog/Verilog RTL Linting Understanding of Clock Domain Crossing RTL synthesis using Synopsys Ability to debug system level issues Ability to script using Perl/Python
Preferred Qualifications:
Experience in verifying designs at system level and block level using constrained random verification. Expert in System Verilog and UVM based verification. Expert in coding SV Test bench, drivers, monitors, scoreboards, checkers. Strong and independent design debugging capability. Strong programming and scripting language capability. Familiar with System Verilog Assertions, Code and Functional Coverage. Understanding of AMBA bus protocols. Good understanding of CPU architecture
Education:
Required: Bachelor's, Electrical Engineering Preferred: Master's, Electrical Engineering or equivalent experience