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Physical design engineer
Ref No.: 17-25521
Location: San Jose, California
Responsible for delivering physical implementation of next generation wifi (802.11) for server and mobile application.
Minimum Qualifications:
At least 6 to 8 plus years with direct physical design experiences. Experience in physical implementation in Synopsys ICC2 from DC-Topo/DCG, Placement, Clock Tree Synthesis and Routing is required. Block level extraction, static timing, signal integrity closure with 14nm finfet below experience. Block level Calibre DRC/LVS closure and advanced DFM requirements closure. EDA CAD tools: Synopsys ICC2/DCT/StarXT, Cadence First Encounter, Mentor Calibre, PrimeTime and PTECO. 1 year in advanced process node of 16 FF.
Preferred Qualifications:
Floorplaning and analysis in Cadence floorplan tools is a plus. ICC2 , 16ff , PNR , STA Master's degree in Electrical Engineering Strong communication skills
Education:
Required: Bachelor's, Electrical Engineering or Computer Science. Preferred: Master's, Electrical Engineering or Computer Science.