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Camera/Imaging Design Verification Engineer
Ref No.: 17-25509
Location: San Diego, California
Design Verification of Camera Image processing IP. The selected candidate is expected to build, maintain and use System Verilog/UVM based testbench to complete verification of various image processing design blocks, interfaces, common infrastructure(AHB, AXI and Bus compatibility) and Use cases. Candidate is expected to independently drive Functional and Code coverage closure for the assigned blocks including performance and power Characterization. Scripting knowledge in Perl and/or python will be required to work with various automation tools that have been deployed. Familiarity with C/C++ will be a bonus in debugging simulations with System Model.
Strong working knowledge of HVLs: System Verilog, C, C++. Experience with methodologies like OVM/UVM. RTL design experience and/or very strong OOPs programming experience. Good written and oral communications skills required. Experience with simulation acceleration tool like Veloce/Palladium is a plus. Working knowledge of Verilog, C/C++, Tcl, Perl, Python, shell-scripting is required.
Strong verification skills: test planning, problem solving, debug, adversarial testing. Multimedia, AXI/AHB Bus and Emulation verification experience is preferred.
Preferred: Master's, Computer Engineering and/or Electrical Engineering Required: Bachelor's