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Mask Layout Designer
Ref No.: 17-25429
Location: Boxborough, Massachusetts
Individual contributor who generates custom RF/Analog for ASICS as part of a larger design team. Must demonstrate proficiency in block level and top level floorplanning, understanding of design rules, device matching, minimization of parasitics, isolation techniques, etc. Run verification programs and debug errors on completed layouts
Minimum Qualifications:
5+ years experience in Analog/RF custom layout design Knowledge of Cadence Virtuoso XL, Calibre, Assura, UNIX and Windows based applications Basic understanding of semiconductor devices as well as CMOS and bipolar processes. Excellent communication skills and ability to work within a team
Preferred Qualifications:
Experience with CMOS technology nodes at 65nm and 180nm is preferred.
Education:
Preferred: Associate's, Electrical Engineering or equivalent experience