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Verification Design Automation Engineer
Ref No.: 17-24649
Location: San Diego, California
Verification Design Automation Engineers are responsible for developing, implementing, and deploying automated methodologies and tool flows that are used to validate a multitude of wireless chips and IP cores/blocks. As part of the Engineering team, this position plays a critical role in driving next-generation verification methodologies through the deployment of semi and full-custom EDA tools that are used widely across the globe by the various ASIC digital design teams. As a key member of the EDA CAD verification design automation team, will develop and contribute directly to technical aspects of many advanced verification methodologies and initiatives. Key areas of focus involve emulation, hardware software co-emulation, simulation acceleration, and UVM methodology. Work closely with cross-functional teams by leveraging domain-specific expertise and sharing/coordinating prototyping efforts, testing, and support. Responsible for developing, implementing, and deploying advanced verification methodologies and flow automations across all chips and IP cores/blocks, as well as across simulation acceleration, emulation, and post silicon validation.
Minimum Qualifications:
Experience evaluating, designing, and deploying EDA tools in the area of functional verification, simulation acceleration and emulation. Prior experience with hardware emulation (EVE, Cadence Palladium, Mentor Veloce, Synopsys HAPS, other FPGA/ASIC-based emulator) of a high-performance processor or SOC. Strong programming capabilities in C/C++, Perl, python, Tcl, Make and Java. Strong Object Oriented programming skills. Experience with methodology development for hardware emulation and simulation acceleration. Good knowledge of Object Oriented Hardware Verification Languages (OO-HVLs) such as SystemVerilog, as well as industry standard hardware description languages (HDLs) like Verilog/VHDL. Experience with relational DB/SQL and No-SQL databases
Preferred Qualifications:
Experience evaluating, designing, and deploying EDA tools in the area of functional verification, simulation acceleration and emulation. Prior experience with hardware emulation (EVE, Cadence Palladium, Mentor Veloce, Synopsys HAPS, other FPGA/ASIC-based emulator) of a high-performance processor or SOC. Strong programming capabilities in C/C++, Perl, python, Tcl, Make and Java. Strong Object Oriented programming skills. Experience with methodology development for hardware emulation and simulation acceleration. Good knowledge of Object Oriented Hardware Verification Languages (OO-HVLs) such as SystemVerilog, as well as industry standard hardware description languages (HDLs) like Verilog/VHDL. Experience with relational DB/SQL and No-SQL databases
Education:
Required: Bachelors of Science degree in Computer Engineering, Computer Science, or Electrical Engineering. Preferred: Masters of Science degree in Computer Engineering, Computer Science, or Electrical Engineering, and/or prior industry experience.