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Senior CMOS RFIC layout designer
Ref No.: 17-24323
Location: Boxborough, Massachusetts
Individual contributor who generates custom RF/Analog for ASICS as part of a larger design team. Must demonstrate proficiency in block level and top level floorplanning, understanding of design rules, device matching, minimization of parasitics, isolation techniques, etc. Run verification programs and debug errors on completed layouts
Minimum Qualifications:
5 years of CMOS RFIC layout experience. Knowledge of Cadence Virtuoso XL, Calibre, Assura, UNIX and Windows based applications Basic understanding of semiconductor devices as well as CMOS and bipolar processes.
Preferred Qualifications:
10 Years, with 65nm and 180nm is preferred.
High school diploma minimum, preferred certificate/associate degree in EE, or CS.