Previous Job
Digital Circuit Card Assembly Design Engineer - SIS
Ref No.: 18-34278
Location: Palm Bay, Florida
Position Type:Contract
Skill Type
Skill Type:Engineering
  • Thorough understanding of digital CCA design process including requirements generation, preliminary design, peer reviews, detailed design, test plan generation, and integration and test.
  • Understand the requirements and architect a digital CCA solution against those requirements including the use of DSP, Microcontroller, FPGA, ASIC, CPLD, Client, DAC, Point of Load (POL), SERDES, Serial (I2C, SPI, etc), and volatile/non-volatile memory (DDRx, SRAM, ROM, Flash, etc) components.
  • Simulate the digital CCA circuits to verify performance, then integrate and test the CCA into the higher level assembly (Signal Integrity simulation).
  • Lead a small team of designers in generating the digital CCA design solutions.
  • Bachelor’s Degree with a minimum of 4 years prior relevant experience or 2 years post-Secondary/Associates Degree with a minimum of 8 years of prior related experience.
  • Experience with design for test and design for manufacturability techniques.
  • Experience with high reliability designs for harsh environments (radiation effects).
  • Experience with high speed memory interfaces (DDRx).
  • Experience with high speed serial protocols (PCI Express, SRIO, Ethernet).
  • Experience with Analog to Digital (AD) and Digital to Analog (DA) interfaces.
  • Experience with control protocols such I2C, SPI, RS-232/422, and SpaceWire.
  • Experience performing Worst-Case Performance and Stress Analysis.
  • Experience with test equipment such as oscilloscopes, spectrum analyzers, logic analyzers, and protocol analyzers.
  • Self-motivated individual with the ability to work and communicate effectively within a development group.
  • Ability to work in a team environment and negotiate solutions with Hardware / Software Engineering and Systems Engineering is preferred.
  • Proficiency with the Cadence toolset for CCA design (Schematic Capture, Constraint-Driven Layout, Simulation, Timing Analysis) is desired